Waveform Options

Posted : admin On 8/22/2021

Spring 2006

Table of Contents

As mentioned above, unlike LTE NR has two options for UL Waveform. One is CP-OFDM (same as DL Waveform) and the other one is DFT-s-OFDM which is same as LTE UL waveform. Transform Precoding is the first step to create DFT-s-OFDM waveform as highlighed below. Whether UE need to use CP-OFDM or DFT-s-OFDM is determined by following RRC Parameter. As well as blank rows (aka Spacer rows) and Time axis. Signal and Bus waveforms are drawn by you, segment by segment, whereas Auto-signal and Auto-bus waveforms are drawn all at once, as a repeated pattern. A diagram can also have: - Title. The Scope menu in the upper-right corner of the waveform monitor provides a variety of display options: RGB Parade: Presents three side-by-side waveform displays that show your video as separate red, green, and blue components. The waveforms are tinted red, green, and blue so that you can easily identify them. Analysis—nearly any type of waveform analysis you can name. Software options integrate seamlessly with the standard tools to extend your capabilities into a wide variety of applications. Our MAUI with OneTouch user interface and deep toolbox is consistently applied across product lines ranging in bandwidth. The easiest way to create simulation stimuli is by adding the desired signals to the Waveform Editor and assigning stimulators that are available from the Stimulators option. There are several options to choose from. The following stimulator types are supported: Clock Stimulator. Typically, the Clock stimulator is used to drive clock signals.

    1. Introduction
    2. Before you start
    3.Compiling and Simulating in post-processing mode
    4.Compiling and Simulating in interactive mode

1. Introduction

Waveform Options Vs

In this class, we will be using the VCS Tool suite from Synopsys. The primary tools we will use will be VCS (Verilog Compiler Simulator)and VirSim, an graphical user interface to VCS for debugging and viewing waveforms. These tools are currently available on the Sun application servers(sunapp1,sunapp2 and sunapp3). Therefore you should ssh to sunapp1, sunapp2 or sunapp3 to use the VCS tool suite.

The methodology of debugging your project design involves three steps:
1) compiling your verilog source code,
2) running the simulation, and
3) viewing the generated waveforms.
The VCS tools will allow you to combine these steps to debug your designinteractively.

VCS works by compiling your Verilog source code into object files, ortranslating them into C source files. VCS invokes a C compiler (cc, gcc,or egcs) to create an executable file that will simulate your design. This simulator can be executed on the command line, and can create a waveformfile. Alternately, the design can be simulated interactively usingVirSim, and the waveforms can be viewed as you step through the simulation.

The rest of this document will give a brief overview of the tools andshow you how to compile and simulate the d-latch example from the EE382NVerilog manual. You should do this tutorial on one of the LRC Sun application servers.

This document is by no means comprehensive. If it doesn'ttell you what you want to know, We suggest you look through the documentationprovided by Synopsis. There is a user guide for VCS available on the LRCSuns in the directory: /usr/local/packages/vcs7.0.1/doc/UserGuide/vcs.pdf. This user guide includes another tutorial for the VCS tools. Thistutorial will explain additional features of the debugging interface thatyou may find useful for this class. There is also a user guidefor VirSim, the interactive debugger, located at /usr/local/packages/vcs7.0.1/doc/UserGuide/VSIM.pdf.

2. Before you start

The VCS package is installed at /usr/local/packages/vcs7.0.1/ onthe Sun application servers. For convenience, we suggest you set the following environmentvariables (you can add this to your .cshrc file):

Waveform Options Explained

setenv VCS_HOME /usr/local/packages/vcs
setenv LM_LICENSE_FILE /usr/local/packages/synopsys/admin/license/key
setenv PATH {$PATH}:/usr/local/packages/vcs/bin

Or for ksh or bash, add the following to your .profile file:

export VCS_HOME=/usr/local/packages/vcs
export LM_LICENSE_FILE=/usr/local/packages/synopsys/admin/license/key
export PATH=$PATH:/usr/local/packages/vcs/bin

Create a directory where you want to put files for this tutorial, andcopy the following files into that directory:
master (a list of all verilog source files neededfor this tutorial)
d_latch.v (This is the same example that wasused in the verilog manual.)

3. Compiling and Simulating in post-processingmode

1. Change to the directory that you created for this tutorial.

2. Compile the verilog source code by typing the following atthe source prompt:
vcs -f master

The -f option means that the file specified (masterin this case) contains a list of command line options for vcs. Inthis case, the command-line options are mostly just a list of library filenames. The following command line would have the same effect:
vcs /home/projects/courses/spring_06/ee382n-15940/lib/time -v /home/projects/courses/spring_06/ee382n-15940/lib/lib1d_latch.v

The -v option before the library file means that only modulesin the file that are actually instantiated (nand2$ and inv1$in this case) will be compiled. When you ran this command,the output should have included the following:

Top Level Modules:
TimeScale is 1 ns / 10 ps
2 of 5 unique modules to generate
2 of 2 modules done
Invoking loader..
simv generation successfully completed

You should now have an executable file called simv in yourworking directory.

3. Execute simv on the command line with no arguments. You should see output from both vcs and the simulation, and it should producea waveform file called d_latch.dump in your working directory.

4. Now we are going to re-invoke vcs to view the waveform. At the prompt, type:
vcs -RPP d_latch.v &

The -RPP option tells vcs that we are opening it in post-processingmode.

5. You should now see Hierarchy window on your screen.

6. In this window, click on Open under the Filemenu option. Change the file type that you want to open to VCD (notVCD+). (VCD (.dump file extension) and VCD+ (.vcdfile extension) files are both waveform files, but VCD files aretext files, and VCD+ files are condensed binary files.)

7. Select and open the file d_latch.dump, and then clickOK. In the hierarchy window, you should see all TOP-level moduleinstantiations: in this case, just latch1, which is the name ofour d-latch. Click on the pink TOP button, and you should see allsignals instantiated at the TOP level in the signal window: d, q, qb,andwe.

8. Click on Waveform under the Window menu option.

9. In the Hierarchy window, highlight all signals in the signallist with the left mouse button. Then with the middle mouse button,drag the selected signals over to the black space in the waveform window. At this point, you should see the waveforms starting at time 0 of the simulation. Most of them will be red at the beginning of the simulation, meaning theyhave the logic value x.

10. In the waveform window, select the menu option Display->Time Scale. Change the display unit to 1 ns and the displayprecision to 100 ps. You can press Ctrl-G a few times to zoom outand see more of the waveforms.

11. You should be able to verify the functionality of the d-latchand determine the propagation delays from the write-enable to the outputsand the d-input to the outputs by examining the waveforms. For thelibrary parts nand2$ and inv1$, the propagation delaysare the same for rising and falling outputs. Is this true of thed-latch?

12. Because we used the system command $dumpvars (0,TOP); in our verilog simulation, we should be able to view all signalsat any hierarchical level of the design. Hence if you go back tothe hierarchy window and click on the plus symbol next to the latch1button, you can traverse down the hierarchy and select more signals toview. If you highlight the button called latch1, you shouldsee all signals and ports for the latch.

13. Before exiting the waveform viewer, you can save your settingsin a configuration file under the File -> Save Configurations option.

4. Compiling and Simulating in interactive mode

1. Now we are going to simulate the design again. Exit VirSimif you have not already. Recompile your source code with the followingcommand line:
vcs -RI -Mupdate -f master &

The -Mupdate is a compile-time option that tells vcs to compileincrementally. When you use this option, it will create a sub-directorycalled csrc. This directory will contain a Makefile andobject files for each module that is compiled. When you compile incrementally,which we suggest you do for your project, only the modules that change betweencompilations will need to be recompiled.

The -RI means we are going to simulate in interactive mode. As soon as the code is compiled, VirSim will be invoked and the simulationwill start.

Waveform Options

The Interactive window of VirSim should have popped up by now. In the History panel, it says $stop at time 0. Whenever you invoke vcs with the -RI option, the simulation will alwaysbe paused at time 0.

2. Open the Hierarchy window by clicking on Hierarchy under the Window menu. Ourdesign had two modules at the highest level: TOP and timeunit. Weare interested in looking at the TOP module. In the menu bar of theHierarchywindow, you will see a little tiny picture of a hierarchy. You canclick on this to select the TOP module.

3. From the main menubar, open the Waveform window, and eitherload your configuration file (using Ctrl-L) or browse through the hierarchyto select signals to view as in part 2.

4. In the Simulator Control panel in the Interactive window,change the Step Time to 1.00 to run the simulation in intervalsof 1 ns. By clicking OK, you can step through the simulation.

Game 129: december 16 2016 the initials game show. 5. You can also step through the simulation until a specifiedtime or until a specified signal (TOP.d, for example) changesvalue. When you simulate interactively, the waveforms are only recordedfor the signals that appear in the Waveform Window. Hence you shouldselect any signals of interest BEFORE the simulation time that you wantto view them. If at any time you want to restart the simulation, selectRe-execor Invoke Sim under the Sim option in the Interactive window.

6. You can also view your source code in the following manner. Click on Source under the Window menu. Then in the Hierarchy window,select a module instance, say TOP, and drag it (using the middle mousebutton) to the large black panel in the Source window. If youwant to edit your code, VCS will invoke a text editor (Edit -> Edit Source).

This should be enough to get you started on Homework 1B. Let usknow if you run into problems.

MDB created Spring 2000
updated 12-Jan-2006

Waveform Compression Options In Eac